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VHDL

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VHDL, aka VHSIC Hardware Description Language, is a hardware description language created in 1983.

#76on PLDB 41Years Old 34kRepos

VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.. Read more on Wikipedia...


Example from hello-world:
use std.textio.all; entity hello_world is end hello_world; architecture behaviour of hello_world is begin process begin write (output, String'("Hello World")); wait; end process; end behaviour;
--Hello World in VHDL ENTITY helloworld IS END helloworld; ARCHITECTURE hw OF helloworld IS BEGIN ASSERT FALSE REPORT "HELLO, WORLD!" SEVERITY NOTE; END hw;
Example from Linguist:
-- VHDL example file library ieee; use ieee.std_logic_1164.all; entity inverter is port(a : in std_logic; b : out std_logic); end entity; architecture rtl of inverter is begin b <= not a; end architecture;
Example from Wikipedia:
process begin wait until START = '1'; -- wait until START is high for i in 1 to 10 loop -- then wait for a few clock periods... wait until rising_edge(CLK); end loop; for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle DATA <= to_unsigned(i, 8); wait until rising_edge(CLK); end loop; -- wait until the output changes wait on RESULT; -- now raise ACK for clock period ACK <= '1'; wait until rising_edge(CLK); ACK <= '0'; -- and so on... end process;
abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not null of on open or others out package port postponed procedure process pure range record register reject rem report return rol ror select severity signal shared sla sll sra srl subtype then to transport type unaffected units until use variable wait when while with xnor xor

Language features

Feature Supported Token Example
Binary Literals โœ“
-- B"[01_]+"
Integers โœ“
-- \d{1,2}#[0-9a-f_]+#?
Floats โœ“
-- (\d+\.\d*|\.\d+|\d+)E[+-]?\d+
Hexadecimals โœ“
-- X"[0-9a-f_]+"
Octals โœ“
-- O"[0-7_]+"
Conditionals โœ“
Functions โœ“
While Loops โœ“
Strings โœ“ "
"Hello world"
Case Insensitive Identifiers โœ“
signals some_signal : integer ;
signal some_other_signal : integer ;
signal result : integer ;
ReSULT <= SOME_SIGNAL + sOME_oTHer_SIGNal ; -- Although totally unrecommended - this is perfectly legal
Print() Debugging โœ“ write
Line Comments โœ“ --
-- A comment
Comments โœ“
Semantic Indentation X
MultiLine Comments X

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