VHDL-AMS is a programming language created in 1993.
| #1604on PLDB | 31Years Old |
VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999). The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.VHDL-AMS is an industry standard modeling language for mixed signal circuits. Read more on Wikipedia...
library IEEE;
use IEEE.math_real.all;
use IEEE.electrical_systems.all;
-- this is the entity
entity DIODE is
generic (iss : current := 1.0e-14;
af : real := 1.0;
kf : real := 0.0);
port (terminal anode, cathode : electrical);
end entity DIODE;
architecture IDEAL of DIODE is
quantity v across i through anode to cathode;
constant vt : voltage := 0.0258;
begin
i == iss * (exp(v/vt) - 1.0);
end architecture IDEAL;| Feature | Supported | Example | Token |
|---|---|---|---|
| Comments | ✓ | -- A comment | |
| Line Comments | ✓ | -- A comment | -- |
| Semantic Indentation | X |