RISC-V - Instruction set architecture

RISC-V is an instruction set architecture created in 2010.

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14Years Old

RISC-V (pronounced "risk-five") is an open instruction set architecture (ISA) based on established reduced instruction set computing (RISC) principles. In contrast to most ISAs, the RISC-V ISA can be freely used for any purpose, permitting anyone to design, manufacture and sell RISC-V chips and software. While not the first open ISA, it is significant because it is designed to be useful in modern computerized devices such as warehouse-scale cloud computers, high-end mobile phones and the smallest embedded systems. Read more on Wikipedia...

Tags: instruction set architecture
Early development of RISC-V happened in University of California Berkeley
See also: (12 related languages) Linux, Verilog, LLVM IR, FreeBSD, JavaScript, Assembly language, MIPS architecture, PowerPC, SPARC, X86, ARM, MMX instruction set

Example from Riju:

	.text
	.global main
main:
	addi a7, x0, 64
	addi a0, x0, 1
	la a1, message
	addi a2, x0, 14
	ecall
	addi a7, x0, 93
	addi a0, x0, 0
	ecall
	.data
message:
	.string "Hello, world!\n"

Example from hello-world:

.data
hello_world: .asciiz "Hello World"

.text
main:   la      a1, hello_world
        li      a0, 4
        ecall

        li      a0, 10
        ecall

Language features

Feature	Supported	Example	Token
Strings	✓	"Hello world"	"